10/31/03 IRFIB7N50APBF smps mosfet hexfet ? power mosfet switch mode power supply ( smps ) uninterruptable power supply high speed power switching high voltage isolation = 2.5kvrms lead-free benefits applications low gate charge qg results in simple drive requirement improved gate, avalanche and dynamic dv/dt ruggedness fully characterized capacitance and avalanche voltage and current effective coss specified ( see an 1001) v dss rds(on) max i d 500v 0.52 ? 6.6a applicable off line smps topologies: two transistor forward notes through are on page 8 s d g half & full bridge convertors to-220 fullp ak power factor correction boost parameter max. units i d @ t c = 25c continuous drain current, v gs @ 10v 6.6 i d @ t c = 100c continuous drain current, v gs @ 10v 4.2 a i dm pulsed drain current 44 p d @t c = 25c power dissipation 60 w linear derating factor 0.48 w/c v gs gate-to-source voltage 30 v dv/dt peak diode recovery dv/dt 6.9 v/ns t j operating junction and -55 to + 150 t stg storage temperature range soldering temperature, for 10 seconds 300 (1.6mm from case ) c mounting torqe, 6-32 or m3 screw 10 lbf?in (1.1n?m) absolute maximum ratings pd - 94805 www.vishay.com 1 document number: 91176
IRFIB7N50APBF parameter min. typ. max. units conditions g fs forward transconductance 6.1 ??? ??? s v ds = 50v, i d = 6.6a q g total gate charge ??? ??? 52 i d = 11a q gs gate-to-source charge ??? ??? 13 nc v ds = 400v q gd gate-to-drain ("miller") charge ??? ??? 18 v gs = 10v, see fig. 6 and 13 t d(on) turn-on delay time ??? 14 ??? v dd = 250v t r rise time ??? 35 ??? i d = 11a t d(off) turn-off delay time ??? 32 ??? r g = 9.1 ? t f fall time ??? 28 ??? r d = 22 ? ,see fig. 10 c iss input capacitance ??? 1423 ??? v gs = 0v c oss output capacitance ??? 208 ??? v ds = 25v c rss reverse transfer capacitance ??? 8.1 ??? pf ? = 1.0mhz, see fig. 5 c oss output capacitance ??? 2000 ??? v gs = 0v, v ds = 1.0v, ? = 1.0mhz c oss output capacitance ??? 55 ??? v gs = 0v, v ds = 400v, ? = 1.0mhz c oss eff. effective output capacitance ??? 97 ??? v gs = 0v, v ds = 0v to 400v dynamic @ t j = 25c (unless otherwise specified) ns parameter typ. max. units e as single pulse avalanche energy ??? 275 mj i ar avalanche current ??? 11 a e ar repetitive avalanche energy ??? 6.0 mj avalanche characteristics s d g parameter min. typ. max. units conditions i s continuous source current mosfet symbol (body diode) ??? ??? showing the i sm pulsed source current integral reverse (body diode) ??? ??? p-n junction diode. v sd diode forward voltage ??? ??? 1.5 v t j = 25c, i s = 11a, v gs = 0v t rr reverse recovery time ??? 510 770 ns t j = 25c, i f = 11a q rr reverse recoverycharge ??? 3.4 5.1 c di/dt = 100a/s t on forward turn-on time intrinsic turn-on time is negligible (turn-on is dominated by l s +l d ) diode characteristics 6.6 44 a parameter typ. max. units r jc junction-to-case ??? 2.1 r ja junction-to-ambient ??? 65 c/w thermal resistance parameter min. typ. max. units conditions v (br)dss drain-to-source breakdown voltage 500 ??? ??? v v gs = 0v, i d = 250a ? v (br)dss / ? t j breakdown voltage temp. coefficient ??? 0.61 ??? v/c reference to 25c, i d = 1ma r ds(on) static drain-to-source on-resistance ??? ??? 0.52 ? v gs = 10v, i d = 4.0a v gs(th) gate threshold voltage 2.0 ??? 4.0 v v ds = v gs , i d = 250a ??? ??? 25 a v ds = 500v, v gs = 0v ??? ??? 250 v ds = 400v, v gs = 0v, t j = 125c gate-to-source forward leakage ??? ??? 100 v gs = 30v gate-to-source reverse leakage ??? ??? -100 na v gs = -30v static @ t j = 25c (unless otherwise specified) i gss i dss drain-to-source leakage current www.vishay.com 2 document number: 91176
IRFIB7N50APBF fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics fig 1. typical output characteristics fig 3. typical transfer characteristics 0.1 1 10 100 0.1 1 10 100 20s pulse width t = 25 c j top bottom vgs 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v 4.5v v , drain-to-source voltage (v) i , drain-to-source current (a) ds d 4.5v 1 10 100 1 10 100 20s pulse width t = 150 c j top bottom vgs 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v 4.5v v , drain-to-source voltage (v) i , drain-to-source current (a) ds d 4.5v 0.1 1 10 100 4.0 5.0 6.0 7.0 8.0 9.0 v = 100v 20s pulse width ds v , gate-to-source voltage (v) i , drain-to-source current (a) gs d t = 25 c j t = 150 c j -60 -40 -20 0 20 40 60 80 100 120 140 160 0.0 0.5 1.0 1.5 2.0 2.5 3.0 t , junction temperature ( c) r , drain-to-source on resistance (normalized) j ds(on) v = i = gs d 10v 11a www.vishay.com 3 document number: 91176
IRFIB7N50APBF fig 8. maximum safe operating area fig 6. typical gate charge vs. gate-to-source voltage fig 5. typical capacitance vs. drain-to-source voltage fig 7. typical source-drain diode forward voltage 0 10 20 30 40 50 0 4 8 12 16 20 q , total gate charge (nc) v , gate-to-source voltage (v) g gs for test circuit see figure i = d 13 6.6a v = 100v ds v = 250v ds v = 400v ds 0.1 1 10 100 0.0 0.4 0.8 1.2 1.6 v ,source-to-drain voltage (v) i , reverse drain current (a) sd sd v = 0 v gs t = 25 c j t = 150 c j 0 400 800 1200 1600 2000 2400 1 10 100 1000 c, capacitance (pf) ds v , drain-to-source voltage (v) a v = 0v, f = 1mhz c = c + c , c shorted c = c c = c + c gs iss gs gd ds rss gd oss ds gd c iss c oss c rss 11a 0.1 1 10 100 1000 10 100 1000 10000 operation in this area limited by r ds(on) single pulse t t = 150 c = 25 c j c v , drain-to-source voltage (v) i , drain current (a) i , drain current (a) ds d 10us 100us 1ms 10ms www.vishay.com 4 document number: 91176
IRFIB7N50APBF fig 10a. switching time test circuit v ds 90% 10% v gs t d(on) t r t d(off) t f fig 10b. switching time waveforms v ds pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 10v + - v dd fig 11. maximum effective transient thermal impedance, junction-to-case fig 9. maximum drain current vs. case temperature 25 50 75 100 125 150 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 t , case temperature ( c) i , drain current (a) c d 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 10 notes: 1. duty factor d = t / t 2. peak t = p x z + t 1 2 j dm thjc c p t t dm 1 2 t , rectangular pulse duration (sec) thermal response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0.50 single pulse (thermal response) www.vishay.com 5 document number: 91176
IRFIB7N50APBF q g q gs q gd v g charge d.u.t. v ds i d i g 3ma v gs .3 f 50k ? .2 f 12v current regulator same type as d.u.t. current sampling resistors + - 10 v fig 13b. gate charge test circuit fig 13a. basic gate charge waveform fig 12c. maximum avalanche energy vs. drain current fig 12b. unclamped inductive waveforms fig 12a. unclamped inductive test circuit t p v (br)dss i as r g i as 0.01 ? t p d.u.t l v ds + - v dd driver a 15v 20v fig 12d. typical drain-to-source voltage vs. avalanche current 580 600 620 640 660 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 a dsav av i , avalanche current (a) v , avalanche voltage (v) 25 50 75 100 125 150 0 100 200 300 400 500 600 starting t , junction temperature ( c) e , single pulse avalanche energy (mj) j as i d top bottom 4.9a 7.0a 11a www.vishay.com 6 document number: 91176
IRFIB7N50APBF p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop re-applied voltage reverse recovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period + - + + + - - - fig 14. for n-channel hexfets * v gs = 5v for logic level devices peak diode recovery dv/dt test circuit r g v dd ? dv/dt controlled by r g ? driver same type as d.u.t. ? i sd controlled by duty factor "d" ? d.u.t. - device under test d.u.t circuit layout considerations ? low stray inductance ? ground plane ? low leakage inductance current transformer * www.vishay.com 7 document number: 91176
IRFIB7N50APBF ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 10/03 data and specifications subject to change without notice. repetitive rating; pulse width limited by max. junction temperature. ( see fig. 11 ) notes: starting t j = 25c, l = 4.5mh r g = 25 ? , i as = 11a. (see figure 12) pulse width 300s; duty cycle 2%. c oss eff. is a fixed capacitance that gives the same charging time as c oss while v ds is rising from 0 to 80% v dss uses irfb11n50a data and test conditions i sd 11a, di/dt 140a/s, v dd v (br)dss , t j 150c t=60s,f=60hz to-220 full-pak package outline dimensions are shown in millimeters (inches) to-220 full-pak part marking information with assembly example: this is an irfi840g lot code 3432 assembled on ww 24 1999 in the assembly line "k" part number lot code assembly international rectifier logo 34 32 924k irfi840g date code year 9 = 1999 week 24 line k note: "p" in assembly line position indicates "lead-free" www.vishay.com 8 document number: 91176
legal disclaimer notice vishay document number: 99901 www.vishay.com revision: 12-mar-07 1 notice the products described herein were acquired by vishay intertechnology, inc., as part of its acquisition of international rectifier?s power control systems (pcs) business, which closed in april 2007. specifications of the products displayed herein are pending review by vishay and are subject to the terms and conditions shown below. specifications of the products displayed herein are subject to change without notice. vishay intertechnology, inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. information contained herein is intended to provide a product description only. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in vishay's terms and conditions of sale for such products, vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and /or use of vishay products including liab ility or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyrigh t, or other intellectual property right. the products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify vishay for any damages resulting from such improper use or sale. international rectifier ? , ir ? , the ir logo, hexfet ? , hexsense ? , hexdip ? , dol ? , intero ? , and powirtrain ? are registered trademarks of international rectifier corporation in the u.s. and other countries. all other product names noted herein may be trademarks of their respective owners.
|
